This is a 9/18 computer
about 1978 ish. This
one
will have a
a real front panel / switches /leds and single instruction step
operation. CPU,64Kb memory+Boot Rom and a
uart will
be
standard.
The cpu is three 128 cell CPLD's and one 128 cell CPLD for the control
logic
and one 64 cell CPLD for data bus swap and buffering.
With a 4 MHZ
clock,instruction times are 1.25 us or 2.50 us long.
Still Under Construction.
8 7 6 5 4 3 2 1 . 9 8 7 6 5 4 3 2 1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
.op. J I X b A C # # # # # # # # # opcode normal, immedate short
# # # # # # # # # # # # # # # # # # immedate word
OP:J=1 j=0
jmp/scc memory
0 X<0 and
1 Z xor
2 S or
3 S|Z ld
4 C add/adc
5 C|Z sub/sbc
6 lea st
7 opr jmp/jsv
