Ben's new 18 bit processor.April 16,2009.

. OP.  . I Z  # # #  # # #  # # #  # # #  # # #
_ _ _  _ _ _  _ _ _  _ _ _  _ _ _  _ _ _  _ _ _

       0              4
0   JSR/OPR    DCA
1   JMP/OPR   AND
2   JZ*/OPR    OR
3   JNZ*/OPR XOR
4   INC            ADD
5   ISZ             ADC
6   DEC           SUB
7   DSZ           SBC
* clears acc

Front panel displays AC,MAR,DATA.
MQ and PC are not displayed.  Address
range is 000 000 to 177 000 with IO at
777 000 to 777 777.

3 128 cell CPLD's are used for  the  bitslice logic
and 2 64 CPLD's are used for control logic and
I/O interfacing. A 2 mhz clock is used, giving a 1.5 us
memory cycle and 300 baud clock for the two uarts.
This gives a mid 70 ish cycle and I/O timing as
well as a resonable memory size 64KW at that time.