This is a 9/18 computer
about 1976 ish. This
one
will have a
a real front panel / switches /leds and single instruction step
operation. CPU,64Kb memory+Boot Rom and a
uart will
be
standard.
The cpu is two 128 cell CPLD's and one 128 cell CPLD for the control
logic.
The sample 48 pin DIP production date is expected to be April
1,1977
with a 5 MHZ clock. Instruction times are 1.6 us to 4.0 us long.
Still Under Construction.
8 7 6 5 4 3 2 1 . 9 8 7 6 5 4 3 2 1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
. OP . I .AC. B .IX. # # # # # # # # # opcode normal - immedate char
# # # # # # # # # # # # # # # # # # immedate word - special
OP: st/ctrl,scc/lea/shift,add/c,sub/c,and/jms/inc*,or/jmp/dec*,xor/jz*/inc2*,ld/jnz*/dec2*
I: Indirect bit
B: Byte sized operand
* direct mode only
